International Symposium on Future of High Performance Green Computing 2018 (HPGC2018)
Professor, Waseda University
Future of High Performance Green Multicore Computing
Multicores have been attracting much attention to improve processing performance and reduce power consumption of computing systems for various application including self-driving automobile, smart home, IoT, deep learning, cancer treatment, image processing, various scientific application including natural disaster simulation, Square Kilometre Array radio telescope and so on. It allows us to reduce power using lower frequency processor cores and increase performance by integrating more cores on a chip including accelerator cores since the power is proportional to the cubes of frequency. To obtain high performance and low power on multicores, co-design of hardware and software, especially parallelizing and power reducing compiler, is very important. This talk introduces importance of a parallelizing and power reducing compiler with its performance and power reduction using DVFS and Clock and Power Gating on various multicores from Intel, IBM, arm, Fujitsu, Tilera, and Renesas for various applications including multimedia, automobile fuel efficient engine control, heavy particle cancer treatment, and earthquake simulation. It also explains importance of hardware and software co-design for next generation high performance Green multicore computing with a memory friendly accelerator that also allows us software short development period and low development cost. As future technologies, the software coherent control and local memory management with multi-dimensional data decomposition technologies are also introduced.
Hironori Kasahara is an IEEE Computer Society President 2018 and a professor in the Department of Computer Science and Engineering at Waseda University. He is an IEEE Fellow, an IPSJ Fellow, a Golden Core Member of the IEEE Computer Society, a professional member of the IEEE Eta Kappa Nu, a member of the Engineering Academy of Japan and the Science Council of Japan. He received a PhD in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at University of California, Berkeley, and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D.
He has served as a chair or member of 250 society and government committees, including a member of the CS Board of Governors and Executive Committee; chair of CS Planning Committee, Constitution & Bylaws Committee, Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, and ASPLOS; board member of IEEE Tokyo section; and member of the Earth Simulator and K supercomputer committees. Kasahara received the CS Golden Core Member Award, IFAC World Congress Young Author Prize, Sakai Special Research Award, and the Japanese Minister’s Science and Technology Prize. He led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 215 papers, 155 invited talks, and 30 patents. His research has appeared in 557 newspaper and Web articles.