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International Workshop on A Strategic Initiative of Computing: Systems and Applications (SISA): Integrating HPC, Big Data, AI and Beyond

Ramaswamy Govindarajan

Ramaswamy Govindarajan

Professor, Supercomputer Education and Research Center (SERC) and Department of Computer Science and Automation
Indian Institute of Science (IISc)


Efficient Compiler and Runtime Systems for Programming Heterogeneous Accelerator-based High Performance Computing Systems

Rapid advances in processor architecture have enabled accelerators such as Graphics Processing Units, Many Integrated Cores, and specialized accelerators, along with multicore processors as major players in increasing the performance of High Performance Computing (HPC) systems. While the performance potentials of these architectures are high, they also pose significant challenges in extracting performance, while ensuring portability and productivity. In this talk, research contributions of our group in developing compiler and runtime systems for synergistic program execution on heterogeneous accelerator-based architectures will be presented. In particular compiler techniques for scheduling, mapping, and managing parallelism in accelerators and hybrid compiler-runtime techniques for memory management and synergistic execution across heterogeneous cores will be presented.


Govindarajan Ramaswamy received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of Science, Bangalore in 1984 and 1989 respectively. He has held postdoctoral research positions and visiting faculty positions at Universities in USA and Canada. Since 1995, he has been with the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore. Currently he is a professor and the chairman of the Supercomputer Education and Research Centre. His research interests are in the areas of High Performance Computing, Compilation Techniques, and Computer Architecture. He has 135 papers in international journals and refereed conference proceedings. He is a Fellow of the Indian National Academy of Engineering and a senior member of IEEE.