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International Workshop on A Strategic Initiative of Computing: Systems and Applications (SISA): Integrating HPC, Big Data, AI and Beyond

Mikhail Smelyanskiy

Mikhail Smelyanskiy

Principal Engineer, Codesign Engineering Director
Data Center Group, Intel
USA

Abstract:

Unexpected Guest Who Crashed the Party: AI Challenge to Traditional HPC

Last six years have seen explosive growth of AI, whose advances, made popular by deep learning, impacted diverse set of domains. It is well known that to train large and complex models using enormous amounts of Big Data in reasonable time requires HPC. In contrast, the target of more traditional HPC has always been numerical simulation, such as CFD, QCD or MD, to name a few. To this end, more traditional HPC vendors have been focusing on building bigger systems to deliver high performance on those applications. At the same time, there has been a recent push integrating simulation, big data analytics and AI to run on the same system. It in this context we will compare and contrast algorithmic and architectural requirements posed by AI and simulation, and expose challenge of unified hardware. We will present several emerging commercial technologies and show how each of them can benefit both application domains. We will conclude with the discussion of several future disruptive technologies, which can also benefit both domains, and whose realization may be closer than is traditionally believed.

Biography:

Mikhail Smelyanskiy is Principal Engineer and director of co-design group within Advanced Development Group at Intel. His group works closely with external HPC and Machine Learning customers to help derive system-level hardware recommendations. Mikhail previously worked at Intel's Parallel Computing Lab, Intel Research, on design, implementation and competitive analysis of parallel algorithms and workloads for the current and future generation parallel processor systems. He made significant contribution to the definition of Intel® Many-Integrated Core (MIC) architecture and the development of the Intel® Xeon Phi™ coprocessor. He leads Intel technical team to become one of five finalists for Gordon-Bell Award in 2014, and to develop world most energy-efficient implementation of HPL that won Intel number one ranking in Green500 in November 2012. He also co-developed world fastest distributed implementation of High-Performance Conjugate Gradient benchmark, which achieved 0.6 Petaflops on Tianhe-2 supercomputer in November, 2014. Dr. Smelyanskiy received PhD in computer science from the University of Michigan.