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International Workshop on A Strategic Initiative of Computing: Systems and Applications (SISA): Integrating HPC, Big Data, AI and Beyond

Hironori Kasahara

Hironori Kasahara

Professor, Computer Science and Engineering
Director, Advanced Multicore Processor Research Institute
Waseda University, Japan
President 2018, IEEE Computer Society

Abstract:

Integrated Development of Parallelizing and Power Reducing Compiler and Multicore Architecture for HPC to Embedded Applications

High performance, low power and easy and efficient parallel software development are key issues for next generation multicore processor systems for embedded application including self-drivng automobile, medical and IoT to scientific applications. This talk introdeces the OSCAR (Optimally Scheduled Advanced MultiprocessoR) multigrain parallelizing and power reducing compiler, OSCAR multicore architecture with vector accelerator desiged to support the compiler optimization and execution performance and power redction using DVFS and power gating of the automibile, medical, multimedia and scientific applications on various multicores including Intel, IBM, Fujitsu, Hitachi, Tilera, ARM, and Renesas.

Biography:

Hironori Kasahara is IEEE Computer Society President-Elect 2017 and President 2018. He received a Ph.D. in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at University of California, Berkeley and the University of Illinois at Urbana–Champaign's Center for Supercomputing R&D. Kasahara has served as a chair or member of 240 society and government committees, including a member of the IEEE Computer Society Board of Governors; chair of CS Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, PPoPP, and ASPLOS; board member of IEEE Tokyo Section; and member of the Earth Simulator committee. He received the CS Golden Core Member Award, IFAC World Congress Young Author Prize, IPSJ Fellow and Sakai Special Research Award, and the Japanese Minister’s Science and Technology Prize, and IEEE Fellow. Kasahara led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 215 papers, 135 invited talks, and 28 patents. His research has been introduced in 544 newspaper and Web articles.