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International Workshop on A Strategic Initiative of Computing: Systems and Applications (SISA): Integrating HPC, Big Data, AI and Beyond

Rick Stevens

Professor Thomas Sterling

Center for Research in Extreme Scale Technologies
School of Informatics and Computing
Indiana University


Runtime System Architecture for Dynamic Graph Processing

Even the highest scale contemporary conventional HPC system architectures are optimized for the basic operations and access patterns of classical matrix and vector processing. These include emphasis on FPU utilization, high data reuse requiring temporal and spatial locality, uniform strides of indexing through regular data structures either dense or sparse. Such systems in the 100 Petaflops performance regime such as the Chinese Sunway Taihu-Light, and the US CORAL Summit and Aurora to be deployed in 2018 in spite of their innovations still are limited in these properties. Emerging classes of new application problems in data analytics, machine learning, and knowledge management demand very different operational properties in response to their highly irregular, sparse, and dynamic behaviors exhibiting little or no data reuse, random access patterns, and meta-data dominated processing. Close examination clearly suggests that at the core of these “big data” applications is dynamic adaptive graph processing which is in some ways diametrically opposite to conventional matrix computing. Of immediate importance is the need to significantly enhance efficiency and scalability as well as user productivity, performance portability, and reduced energy. Key to this is the introduction of powerful runtime system software for the exploitation of real-time system status information to support dynamic adaptive resource management and task scheduling. But software alone will be insufficient for extreme-scale where near fine-grained parallelism is necessary and software overheads will bound efficiency and scalability. A new era of architecture research is beginning in the combined domains of accelerator hardware for both graph processing and runtime systems. This presentation will discuss the nature of the computational challenges, examples and experiments with state of the art runtime system software HPX-5, and future directions in hardware architecture support for exascale runtime-assisted big data computation. Questions and comments from the audience will be welcome throughout the talk.


Dr. Thomas Sterling holds the position of Professor of Electrical Engineering at the Indiana University (IU) School of Informatics and Computing Department of Intelligent Systems Engineering (ISE) as well as serves as Director of the IU Center for Research in Extreme Scale Technologies (CREST). Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow, Dr. Sterling has engaged in applied research in parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing for which he shared the Gordon Bell Prize in 1997. He led the HTMT Project sponsored by multiple agencies to explore advanced technologies and their implication for high-end computer system architectures. Other research projects in which he contributed included the DARPA DIVA PIM architecture project with USC-ISI, the DARPA HPCS program sponsored Cray-led Cascade Petaflops architecture, and the Gilgamesh high-density computing project at NASA JPL. Sterling is currently involved in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding the development of future generation Exascale computing systems. ParalleX is currently the conceptual centerpiece of the XPRESS project as part of the DOE X-stack program and has been demonstrated via the proof-of-concept HPX+ runtime system software. Dr. Sterling is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS. He is also currently working on the textbook, “High Performance Computing”, to be published by Morgan-Kaufmann in 2017.