Frontier of
Embodiment Informatics:
ICT and Robotics

Top Global University Project: Waseda Goes Global - A Plan to Build a
Worldwide Academic Network that is Open, Dynamic and Diverse

Lecture from Professor Josep Torrellas, the University of Illinois at Urbana-Champaign on October 19, 2018

Date & Time 19 October 2018 (Friday) 16:30 – 18:00
Title Extreme Energy-Efficient Computer Architectures
Venue Room 102, Green Computing Systems Research and Development Center, Waseda University(Map
Target participants All Waseda students, faculty members, and the general public
Participant fee None
Organizer The Frontier of Embodiment Informatics: ICT and Robotics, TGU (Top Global University), Waseda University
Advanced Multicore Processor Research Institute, Waseda University
Sponsor IEEE Eta Kappa Nu Waseda University Student Chapter Mu Tau
IEEE Multicore STC

Extreme Energy-Efficient Computer Architectures

Energy and power are the main constraints in computer architecture today and in the foreseable future. Unfortunately, there is no silver-bullet technique that can single-handedly solve the problem. Instead, we need to apply a set of technologies that, in combination, can improve energy efficiency substantially. This talk presents some of these technologies. Cores need to be designed to flexibly operate at a wide range of voltages, and techniques such as power gating and voltage speculation need to be widespread. New formal controllers can manage multiple parameters concurrently for minimal resource waste. Further, if novel devices can be integrated with conventional CMOS, highly efficient architectures can be designed.

Prof. Josep Torrellas

Josep Torrellas

Biography

Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He leads the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He has been the director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He is a Fellow of IEEE, ACM, and AAAS. He received the 2015 IEEE CS Technical Achievement Award, and the 2017 UIUC Campus Award for Excellence in Graduate Student Mentoring.